Features, Applications

HIGH SPEED: tPD = 13ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 155

DESCRIPTION The is an high speed CMOS QUAD 2-INPUT NAND GATE fabricated with silicon gate C2MOS technology. It features dual to 4 line demultiplexers with individual strobe inputs (1G and 2G), individual data inputs (1C and 2C) and common binary address inputs (A and B). When both decoders are enabled by the strobes, the inverted output of 1C data and non-inverted output of 2C data will be brought to the select

output pins of each sections. to 8 line demultiplexer can also easily built up by providing a data signal to both 1C and 2C inputs; the output order from the msb 2Y1, 2Y0. This device can be used to 4 line decoder to 8 line decoder when 1C is held high and 2C is held low. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN No SYMBOL to 2Y3 GND VCC NAME AND FUNCTION Data Inputs Strobe Inputs Common Data Inputs Outputs Ground (0V) Positive Supply Voltage

This logic diagram has not be used to estimate propagation delays

Symbol VCC VI VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to VCC -0.5 to VCC +150 300 Unit mW °C

ICC or IGND DC VCC or Ground Current PD Power Dissipation Tstg TL Storage Temperature Lead Temperature (10 sec)

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied at 65 °C; derate by 10mW/°C from to 85°C