High Performance Current Mode PWM Controller

TRIMMED OSCILLATOR DISCHARGE CURRENT MODE OPERATION TO 500kHz AUTOMATIC FEED FORWARD COMPENSATION LATCHING PWM FOR CYCLE-BY-CYCLE CURRENT LIMITING INTERNALLY TRIMMED REFERENCE WITH UNDERVOLTAGE LOCKOUT HIGH CURRENT TOTEM POLE OUTPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS LOW START-UP CURRENT 0.5mA) DOUBLE PULSE SUPPRESSION

comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the offstate. Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC3842A and UC3844A have UVLO thresholds of 16V (on) and 10V (off), ideally suited off-line applications The corresponding thresholds for the UC3843A and UC3845A are 8.5 V and 7.9V. The UC3842A and UC3843A can operate to duty cycles approaching 100%. A range of the zero % is obtained by the UC3844A and UC3845A by the addition of an internal toggle flip flop which blanks the output off every other clock cycle.

DESCRIPTION The UC384xA family of control ICs provides the necessary features to implement off-line to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include a trimmed oscillator for precise DUTY CYCLE CONTROL under voltage lockout featuring start-up current less than 0.5mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM

BLOCK DIAGRAM (toggle flip flop used only in UC3844A and UC3845A)
7 34V GROUND 5 UVLO S/R 5V REF INTERNAL BIAS VREF GOOD LOGIC RT/CT 4 OSC ERROR AMP. 1V T
Symbol IO EO Parameter Supply Voltage (low impedance source) Supply Voltage (Ii < 30mA) Output Current Output Energy (capacitive load) Analog Inputs (pins 2, 3) Error Amplifier Output Sink Current Ptot Tstg TJ TL Power Dissipation at Tamb 25 °C (Minidip) Power Dissipation at Tamb °C (SO8) Storage Temperature Range Junction Operating Temperature Lead Temperature (soldering 10s) Value 30 Self Limiting mW °C Unit V

* All voltages are with respect to pin 5, all currents are positive into the specified terminal.
No Function COMP VFB ISENSE RT/CT GROUND OUTPUT VCC Vref Description This pin is the Error Amplifier output and is made available for loop compensation. This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. The oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and cpacitor CT to ground. Operation 500kHz is possible. This pin is the combined control circuitry and power ground. This output directly drives the gate of a power MOSFET. Peak currents to 1A are sourced and sunk by this pin. This pin is the positive supply of the control IC. This is the reference output. It provides charging current for capacitor C T through resistor RT.

Symbol Rth j-amb Description Thermal Resistance Junction-ambient. max. Minidip SO8 150 Unit °C/W
ELECTRICAL CHARACTERISTICS ( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85°C for 0 < Tamb < 70°C for = 15V (note = 3.3nF)

REFERENCE SECTION VREF Output Voltage VREF Line Regulation Load Regulation
Io 20mA (Note 2) Line, Load, Temperature = 25°C (note 2) Tamb = (note 125°C, 1000Hrs
VREF/T Temperature Stability Total Output Variation eN Output Noise Voltage Long Term Stability ISC Output Short Circuit

OSCILLATOR SECTION fOSC Frequency fOSC/V fOSC/T VOSC Idischg Frequency Change with Temp. Oscillator Voltage Swing

Discharge Current (VOSC = 2.5V VFB 15K to Ground 15K to Pin 8 (note = 5V (note Vi 25V (note 3)
ERROR AMP SECTION Input Voltage Ib BW PSRR Io Input Bias Current AVOL Unity Gain Bandwidth Power Supply Rejec. Ratio Output Sink Current Output Source Current VOUT High VOUT Low CURRENT SENSE SECTION GV Gain V3 SVR Ib Maximum Input Signal Supply Voltage Rejection Input Bias Current Delay to Output